1. Field of the Invention
The present invention relates to a technology for forming a drain region with high accuracy in order to realize an improvement of breakdown voltage and a reduction of on-resistance.
2. Description of the Related Art
In a known method of manufacturing a semiconductor device, first, a LOCOS (local oxidation of silicon) oxide film is formed in drain regions which are formed so as to have double-diffused structures. At this time, bird's beak shapes of the LOCOS oxide film which are located on the drain region sides are formed so as to have gradual slopes and large sizes. Further, ions of an impurity are implanted through the upper surface of the LOCOS oxide film at a high acceleration voltage by utilizing the bird's beak shapes of the LOCOS oxide film, and then diffused. By this manufacturing method, a low-concentration diffusion layer is formed which is deeply diffused in the drain regions. Subsequently, using the LOCOS oxide film, an impurity is implanted through the surface of the low-concentration diffusion layer by a self-alignment technique to form a high-concentration diffusion layer in the drain regions. This technology is described for instance in pp. 8-10, FIGS. 5-9 in Japanese Patent Application Publication No. 2003-309258.
As described above, in the known semiconductor device manufacturing method, a silicon oxide film and a silicon nitride film are selectively formed on the surface of an epitaxial layer in the region in which the LOCOS oxide film is to be formed. Then, after the LOCOS oxide film is formed, the drain regions are formed by ion implantation through the upper surfaces of the bird's beaks of the LOCOS oxide film. Accordingly, there is the problem that alignment accuracy is low because the regions for forming the drain regions are deviated because of mask misalignment in the formation of the LOCOS oxide film, the film thicknesses, shapes, and the like of the bird's beak portions.
Further, if the drain regions are formed to the vicinity of a back-gate region which is formed to overlap a source region, there occurs the problem that the breakdown voltage deteriorates. On the other hand, if the drain regions are formed far from the back-gate region, there occurs the problem that the on-resistance increases. That is, the drain regions need to be formed with high accuracy in consideration of the breakdown voltage, the on-resistance, and the like. However, as described above, there is the problem that it is difficult to realize a desired breakdown voltage and a desired on-resistance because alignment accuracy for the drain regions is low.
Moreover, on the surface of the epitaxial layer, the silicon oxide film and the silicon nitride film for forming the LOCOS oxide film are deposited first. After the LOCOS oxide film is formed, the silicon oxide film and the silicon nitride film are removed, and a gate oxide film and a polysilicon film for gate electrodes are deposited. This manufacturing method has the problem that manufacturing cost is high because a manufacturing process is complicated.